Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables

Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models with which the gate can be replaced when its output is steady HIGH or steady LOW. Traditional ASIC libraries are characterized for slew and delay for static timing signoff. These represent the behavior of gates during switching. However, for noise analysis we require models for gates when the output is stable. The objective of this work is to derive such models from circuits characterized for slew. This enables a designer to stay in the familiar STA (Static Timing Analysis) environment and perform noise analysis. We write the non-linear current-voltage relationship of the conducting PMOS or NMOS transistor. This relationship is interpreted as a non-linear resistor. We use it to compute output transition times in a simplified circuit. These transition times are matched with appropriate entry in slew table for...

• Type: Conference
• Year: 2004
• Where: VLSID
• Authors: Shabbir H. Batterywala, Narendra V. Shenoy
• Keywords: Computer Architecture, Non-linear Port Resistance, Non-linear Resistor, Steady State Resistance, VLSID 2004