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CODES
2005
IEEE
14 years 2 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
CODES
2005
IEEE
14 years 2 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 2 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ICALT
2005
IEEE
14 years 2 months ago
ActiveTutor
In this paper we present an architecture dedicated to an intelligently assisted educational tool which integrates within a unified framework software rational agents both at the m...
Jean Pierre Fournier
ICNP
2005
IEEE
14 years 2 months ago
Robust Multiclass Signaling Overload Control
We propose multi-class signaling overload control algorithms, for telecommunication switches, that are robust against different input traffic patterns and system upgrades. In ord...
Sneha Kumar Kasera, José Pinheiro, Catherin...
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