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DAC
2000
ACM
16 years 5 months ago
COSY communication IP's
The Esprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. ...
Erwin A. de Kock, Frédéric Pé...
DAC
2000
ACM
16 years 5 months ago
MINFLOTRANSIT: min-cost flow based transistor sizing tool
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
DAC
2002
ACM
16 years 5 months ago
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...
DAC
2005
ACM
16 years 5 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
DAC
2006
ACM
16 years 5 months ago
Timing driven power gating
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...
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