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ARC
2007
Springer
102views Hardware» more  ARC 2007»
15 years 8 months ago
Reconfigurable Hardware Acceleration of Canonical Graph Labelling
Many important algorithms in computational biology and related subjects rely on the ability to extract and to identify sub-graphs of larger graphs; an example is to find common fun...
David B. Thomas, Wayne Luk, Michael Stumpf
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 8 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
ASPDAC
2007
ACM
110views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Fast Placement Optimization of Power Supply Pads
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...
Yu Zhong, Martin D. F. Wong
CEC
2007
IEEE
15 years 8 months ago
Evolving hypernetwork classifiers for microRNA expression profile analysis
Abstract-- High-throughput microarrays inform us on different outlooks of the molecular mechanisms underlying the function of cells and organisms. While computational analysis for ...
Sun Kim, Soo-Jin Kim, Byoung-Tak Zhang
CEC
2009
IEEE
15 years 8 months ago
JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
Olivier Brousse, Jérémie Guillot, Th...
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