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ASPLOS
2009
ACM
14 years 7 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
EUROSYS
2007
ACM
14 years 3 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 1 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
WCNC
2008
IEEE
14 years 1 months ago
Unequal Error Protection Irregular Over-Complete Mapping for Wavelet Coded Wireless Video Telephony Using Iterative Source and C
— Since the different bits of the compressed video sequence produced by the BBC’s wavelet-based video codec exhibit different error sensitivity, efficient Unequal Error Protec...
Anh Quang Pham, Lie-Liang Yang, Lajos Hanzo
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
14 years 23 days ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...