Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
xample-Guided Abstraction Refinement for Symbolic Model Checking EDMUND CLARKE YUAN LU Carnegie Mellon University, Pittsburgh, Pennsylvania Broadcom Co., San Jose, California ORNA ...
Edmund M. Clarke, Orna Grumberg, Somesh Jha, Yuan ...