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FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 3 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ICRA
2005
IEEE
146views Robotics» more  ICRA 2005»
14 years 3 months ago
Probabilistic Gaze Imitation and Saliency Learning in a Robotic Head
— Imitation is a powerful mechanism for transferring knowledge from an instructor to a na¨ıve observer, one that is deeply contingent on a state of shared attention between the...
Aaron P. Shon, David B. Grimes, Chris Baker, Matth...
IEEEPACT
2005
IEEE
14 years 3 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
IEEEPACT
2005
IEEE
14 years 3 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
TRIDENTCOM
2005
IEEE
14 years 3 months ago
Divide and Conquer: PC-Based Packet Trace Replay at OC-48 Speeds
Today’s Internet backbone networking devices need to be tested under realistic traffic conditions at transmission rates of OC-48 and above. While commercially available synthet...
Tao Ye, Darryl Veitch, Gianluca Iannaccone, Suprat...