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99
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IPPS
2007
IEEE
15 years 8 months ago
Using an FPGA for Fast Bit Accurate SoC Simulation
In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
LCN
2006
IEEE
15 years 8 months ago
Accuracy-Speedup Tradeoffs for a Time-Parallel Simulation of Wireless Ad hoc Networks
We introduce a scalable algorithm for time-parallel simulations of wireless ad hoc networks and report on our results. Our approach decomposes the simulation into overlapping temp...
Guoqiang Wang, Damla Turgut, Ladislau Böl&oum...
HPCA
1999
IEEE
15 years 6 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
115
Voted
CHI
2006
ACM
16 years 2 months ago
Collaborative simulation interface for planning disaster measures
We introduce a disaster simulation system that supports collaborative planning of disaster measures. While several simulation tools are available for examination and evaluation of...
Kazue Kobayashi, Atsunobu Narita, Mitsunori Hirano...
132
Voted
IPPS
2003
IEEE
15 years 7 months ago
The CoGenT Project: Co-Generating Compilers and Simulators for Dynamically Compiled Languages
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
J. Eliot B. Moss, Charles C. Weems, Timothy Richar...