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IEEEPACT
2005
IEEE
15 years 10 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
IRI
2005
IEEE
15 years 10 months ago
Data-knowledge-context: an application model for collaborative work
For many years, researchers and software developers have been seeking to develop systems and applications to enable efficient and effective group work and organizational memory. ...
Lee A. Iverson
ISPASS
2005
IEEE
15 years 10 months ago
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, L...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 10 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
MSS
2005
IEEE
62views Hardware» more  MSS 2005»
15 years 10 months ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
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