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DAC
2009
ACM
14 years 11 months ago
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang
ASPLOS
2010
ACM
14 years 4 months ago
Power routing: dynamic power provisioning in the data center
Data center power infrastructure incurs massive capital costs, which typically exceed energy costs over the life of the facility. To squeeze maximum value from the infrastructure,...
Steven Pelley, David Meisner, Pooya Zandevakili, T...
ICC
2008
IEEE
135views Communications» more  ICC 2008»
14 years 4 months ago
Using Soft-Line Recursive Response to Improve Query Aggregation in Wireless Sensor Networks
— In large Wireless Sensor Networks (WSNs), each hop might incur varying delays due to medium access contention, transmission and computation delays. Fast and efficient query re...
Xiaoming Lu, Matt Spear, Karl N. Levitt, Norman S....
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 4 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
LCTRTS
2007
Springer
14 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...