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VLSID
2002
IEEE
79views VLSI» more  VLSID 2002»
14 years 10 months ago
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, ...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
14 years 2 months ago
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach
In this paper, an analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test a...
Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
SOFSEM
2012
Springer
12 years 5 months ago
Randomized Group Testing Both Query-Optimal and Minimal Adaptive
The classical group testing problem asks to determine at most d defective elements in a set of n elements, by queries to subsets that return Yes if the subset contains some defecti...
Peter Damaschke, Azam Sheikh Muhammad
SCALESPACE
2009
Springer
14 years 4 months ago
Geodesically Linked Active Contours: Evolution Strategy Based on Minimal Paths
The proposed method is related to parametric and geodesic active contours as well as minimal paths, in the context of image segmentation 1 . Our geodesically linked active contour ...
Julien Mille, Laurent D. Cohen
SIAMCOMP
1998
114views more  SIAMCOMP 1998»
13 years 9 months ago
Maximum k-Chains in Planar Point Sets: Combinatorial Structure and Algorithms
A chain of a set P of n points in the plane is a chain of the dominance order on P. A k-chain is a subset C of P that can be covered by k chains. A k-chain C is a maximum k-chain ...
Stefan Felsner, Lorenz Wernisch