4401 search results - page 69 / 881 » Computing with Default Logic |
117
Voted
VLSID
1999
IEEE
15 years 6 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
143
Voted
FDL
2003
IEEE
15 years 7 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
88
Voted
ICLP
2007
Springer
15 years 8 months ago
2007
Springer
LPAR
2007
Springer
15 years 8 months ago
2007
Springer
88
Voted
VSTTE
2005
Springer
15 years 8 months ago
2005
Springer