4401 search results - page 725 / 881 » Computing with Default Logic |
VSTTE
2012
Springer
12 years 5 months ago
2012
Springer
Motivated by the problem of deciding verification conditions for the verification of functional programs, we present new decision procedures for automated reasoning about functio...
DAC
2012
ACM
12 years 16 days ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
DAC
2012
ACM
12 years 16 days ago
2012
ACM
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
DAC
2012
ACM
12 years 16 days ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
GIS
2007
ACM
14 years 11 months ago
2007
ACM
We have developed Environmental Scenario Search Engine (ESSE) for parallel data mining of a set of conditions inside distributed, very large databases from multiple environmental ...