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159
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VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
16 years 3 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
HPDC
2003
IEEE
15 years 7 months ago
Optimizing GridFTP through Dynamic Right-Sizing
In this paper, we describe the integration of dynamic right-sizing — an automatic and scalable buffer management technique for enhancing TCP performance — into GridFTP, a sub...
Sunil Thulasidasan, Wu-chun Feng, Mark K. Gardner
PODS
1994
ACM
138views Database» more  PODS 1994»
15 years 6 months ago
Dyn-FO: A Parallel, Dynamic Complexity Class
Traditionally, computational complexity has considered only static problems. Classical Complexity Classes such as NC, P, and NP are de ned in terms of the complexity of checking {...
Sushant Patnaik, Neil Immerman
124
Voted
BMCBI
2007
233views more  BMCBI 2007»
15 years 2 months ago
160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...
Isaac T. S. Li, Warren Shum, Kevin Truong
126
Voted
JCB
2006
144views more  JCB 2006»
15 years 2 months ago
Modeling Virus Self-Assembly Pathways: Avoiding Dynamics Using Geometric Constraint Decomposition
We develop a model for elucidating the assembly pathways by which an icosahedral viral shell forms from 60 identical constituent protein monomers. This poorly understood process a...
Meera Sitharam, Mavis Agbandje-Mckenna