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ITC
1999
IEEE
105views Hardware» more  ITC 1999»
13 years 11 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
FDTC
2007
Springer
82views Cryptology» more  FDTC 2007»
14 years 1 months ago
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations
Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Kar...