62 search results - page 4 / 13 » Concurrent Fault Detection in Random Combinational Logic |
ITC
1995
IEEE
13 years 10 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
ITC
1994
IEEE
13 years 10 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
ISQED
2010
IEEE
13 years 8 months ago
2010
IEEE
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
ACST
2006
13 years 8 months ago
2006
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of m...