On Using Machine Learning for Logic BIST

This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo–random sequence as in existing techniques, but rather are used to produce relevant features allowing to generate directed random test patterns that detect random pattern resistant faults as well as easy–to–test faults. A BIST implementation that uses a classical LFSR plus a small amount of mapping logic is also proposed in this paper. Results are shown for benchmark circuits which indicate that our technique can reduce the weighted or pseudo–random test length required for a particular fault coverage. Other results are given to show the possible trade off between hardware overhead and test sequence length. An encouraging point is that...

• Type: Conference
• Year: 1997
• Where: ITC
• Authors: Christophe Fagot, Patrick Girard, Christian Landrault
• Keywords: Hardware, ITC 1997, Pattern Resistant Faults, Test Patterns, Test Sequence