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114
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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 9 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
120
Voted
GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
15 years 7 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
DATE
2005
IEEE
105views Hardware» more  DATE 2005»
15 years 8 months ago
Mutation Sampling Technique for the Generation of Structural Test Data
Our goal is to produce validation data that can be used as an efficient (pre) test set for structural stuck-at faults. In this paper, we detail an original test-oriented mutation ...
Mathieu Scholivé, Vincent Beroulle, Chantal...
122
Voted
SE
2008
15 years 4 months ago
Automatic Test Case Generation from UML Models and OCL Expressions
: In this paper, we discuss one approach of automated test case generation from UML models and OCL expressions. We show how to use UML and OCL to support several coverage criteria....
Stephan Weißleder, Dehla Sokenou
100
Voted
ECAI
2008
Springer
15 years 4 months ago
Test Generation for Model-Based Diagnosis
This article formalises the dual problem to model-based diagnosis (MBD), i.e., generating tests to isolate multiple simultaneous faults. Using a standard propositional MBD framewo...
Gregory M. Provan