734 search results - page 116 / 147 » Configurable Transactional Memory |
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Addressing this challenge requires adva...
ASPLOS
2012
ACM
12 years 3 months ago
2012
ACM
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...
SC
2009
ACM
14 years 7 days ago
2009
ACM
In order to understand the complex physics of mother nature, physicist often use many approximations to understand one area of physics and then write a simulation to reduce these ...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...