734 search results - page 126 / 147 » Configurable Transactional Memory |
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
The advent of multicore processors requires mainstream concurrent programming languages with high level concurrency constructs and effective debugging techniques. Unfortunately, m...
ISPASS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
HASKELL
2005
ACM
14 years 1 months ago
2005
ACM
Multi-core processors are coming, and we need ways to program them. The combination of purely-functional programming and explicit, monadic threads, communicating using transaction...
EUROPKI
2004
Springer
14 years 28 days ago
2004
Springer
Abstract. The Peer-to-Peer Wireless Network Confederation (P2PWNC) is designed to be an open self-organizing Wireless LAN (WLAN) roaming association where users from one WLAN can a...