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» Configurable Transactional Memory
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ASPLOS
2011
ACM
13 years 7 days ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
ICSE
2003
IEEE-ACM
14 years 8 months ago
The Deployer's Problem: Configuring Application Servers for Performance and Reliability
Frameworks such as J2EE are designed to simplify the process of developing enterprise applications by handling much of the complexity of concurrency, transaction, and persistence ...
Mukund Raghavachari, Darrell Reimer, Robert D. Joh...
IPPS
2007
IEEE
14 years 2 months ago
A Key-based Adaptive Transactional Memory Executor
Software transactional memory systems enable a programmer to easily write concurrent data structures such as lists, trees, hashtables, and graphs, where non-conflicting operation...
Tongxin Bai, Xipeng Shen, Chengliang Zhang, Willia...
HASE
2007
IEEE
14 years 3 months ago
Systems Architectures for Transactional Network Interface
Systems such as software transactional memory and some exception handling techniques use transactions. However, a typical limitation of such systems is that they do not allow syst...
Manish Marwah, Shivakant Mishra, Christof Fetzer
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 2 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy