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ERSA
2010
159views Hardware» more  ERSA 2010»
13 years 6 months ago
Acceleration of FPGA Fault Injection Through Multi-Bit Testing
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
Grzegorz Cieslewski, Alan D. George, Adam Jacobs
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 9 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
DDECS
2006
IEEE
108views Hardware» more  DDECS 2006»
14 years 2 months ago
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo ...
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
14 years 2 months ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
CORR
2010
Springer
108views Education» more  CORR 2010»
13 years 8 months ago
An Analysis of Transaction and Joint-patent Application Networks
Many firms these days, forced by increasing international competition and an unstable economy, are opting to specialize rather than generalize as a way of maintaining their compet...
Hiroyasu Inoue