Sciweavers

734 search results - page 49 / 147
» Configurable Transactional Memory
Sort
View
SYSTOR
2009
ACM
14 years 3 months ago
Transactifying Apache's cache module
Apache is a large-scale industrial multi-process and multithreaded application, which uses lock-based synchronization. We report on our experience in modifying Apache’s cache mo...
Haggai Eran, Ohad Lutzky, Zvika Guz, Idit Keidar
APCSAC
2004
IEEE
14 years 14 days ago
Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
Philip Machanick
DAC
2012
ACM
11 years 11 months ago
STM concurrency control for embedded real-time software with tighter time bounds
We consider software transactional memory (STM) concurrency control for multicore real-time software, and present a novel contention manager (CM) for resolving transactional conï¬...
Mohammed El-Shambakey, Binoy Ravindran
DATE
2010
IEEE
110views Hardware» more  DATE 2010»
14 years 1 months ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
SIGMOD
2008
ACM
190views Database» more  SIGMOD 2008»
14 years 8 months ago
OLTP through the looking glass, and what we found there
Online Transaction Processing (OLTP) databases include a suite of features -- disk-resident B-trees and heap files, locking-based concurrency control, support for multi-threading ...
Stavros Harizopoulos, Daniel J. Abadi, Samuel Madd...