Sciweavers

734 search results - page 87 / 147
» Configurable Transactional Memory
Sort
View
LCPC
2007
Springer
14 years 3 months ago
Automatic Communication Performance Debugging in PGAS Languages
Recent studies have shown that programming in a Partition Global Address Space (PGAS) language can be more productive than programming in a message passing model. One reason for th...
Jimmy Su, Katherine A. Yelick
DAC
2008
ACM
14 years 9 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
HPCA
2001
IEEE
14 years 9 months ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...
COLCOM
2007
IEEE
14 years 3 months ago
Privacy protection on sliding window of data streams
—In many applications, transaction data arrive in the form of high speed data streams. These data contain a lot of information about customers that needs to be carefully managed ...
Weiping Wang 0001, Jianzhong Li, Chunyu Ai, Yingsh...
IEEEPACT
2005
IEEE
14 years 2 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...