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FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 11 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 2 months ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George
FCCM
1998
IEEE
149views VLSI» more  FCCM 1998»
13 years 11 months ago
Configuration Compression for the Xilinx XC6200 FPGA
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
Scott Hauck, Zhiyuan Li, Eric J. Schwabe
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
13 years 11 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
ARC
2008
Springer
89views Hardware» more  ARC 2008»
13 years 9 months ago
A Networked, Lightweight and Partially Reconfigurable Platform
Abstract. In this paper we present a networked lightweight and partially reconfigurable platform assisted by a remote bitstreams server. We propose a software and hardware architec...
Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet