Sciweavers

35 search results - page 6 / 7
» Configuration bitstream compression for dynamically reconfig...
Sort
View
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
14 years 5 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
MATA
2004
Springer
199views Communications» more  MATA 2004»
14 years 1 months ago
Configuration Management for Networked Reconfigurable Embedded Devices
Distribution of product updates to embedded devices can increase product lifetimes for consumers and boost revenues for vendors. Dynamic provisioning of application solutions to e...
Timothy O'Sullivan, Richard Studdert
JSA
2002
130views more  JSA 2002»
13 years 8 months ago
Reconfigurable models of finite state machines and their implementation in FPGAs
This paper examines some models of FSMs that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a wa...
Valery Sklyarov
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 10 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
IPPS
2006
IEEE
14 years 2 months ago
Dedicated module access in dynamically reconfigurable systems
Modern FPGAs, such as the Xilinx Virtex-II Series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) du...
Jens Hagemeyer, Boris Kettelhoit, Mario Porrmann