15 search results - page 3 / 3 » Configuring multiple scan chains for minimum test time |
DELTA
2004
IEEE
13 years 11 months ago
2004
IEEE
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
ITC
2003
IEEE
14 years 29 days ago
2003
IEEE
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
ISQED
2002
IEEE
14 years 18 days ago
2002
IEEE
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
RCIS
2010
13 years 6 months ago
2010
—The strategies for mining frequent itemsets, which is the essential part of discovering association rules, have been widely studied over the last decade. In real-world datasets,...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...