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ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 1 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
DATE
2004
IEEE
105views Hardware» more  DATE 2004»
14 years 24 days ago
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
LICS
1997
IEEE
14 years 18 days ago
How Much Memory is Needed to Win Infinite Games?
We consider a class of infinite two-player games on finitely coloured graphs. Our main question is: given a winning condition, what is the inherent blow-up (additional memory) of ...
Stefan Dziembowski, Marcin Jurdzinski, Igor Waluki...
ICPP
2008
IEEE
14 years 3 months ago
Implementing and Exploiting Inevitability in Software Transactional Memory
—Transactional Memory (TM) takes responsibility for concurrent, atomic execution of labeled regions of code, freeing the programmer from the need to manage locks. Typical impleme...
Michael F. Spear, Michael Silverman, Luke Dalessan...
ROBOCOMM
2007
IEEE
14 years 3 months ago
Shared memories: a trail-based coordination server for robot teams
Abstract—Robust, dependable and concise coordination between members of a robot team is a critical ingredient of any such collective activity. Depending on the availability and t...
George Roussos, Dikaios Papadogkonas, J. Taylor, D...