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» Constant Multipliers for FPGAs
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PDPTA
2000
14 years 10 days ago
Constant Multipliers for FPGAs
This paper presents a survey of techniques to implement multiplications by constants on FPGAs. It shows in particular that a simple and well-known technique, canonical signed recod...
Florent de Dinechin, Vincent Lefèvre
ASAP
2008
IEEE
96views Hardware» more  ASAP 2008»
14 years 5 months ago
Integer and floating-point constant multipliers for FPGAs
Reconfigurable circuits now have a capacity that allows them to be used as floating-point accelerators. They offer massive parallelism, but also the opportunity to design optimi...
Nicolas Brisebarre, Florent de Dinechin, Jean-Mich...
TC
2008
13 years 11 months ago
Automatic Generation of Modular Multipliers for FPGA Applications
Since redundant number systems allow for constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed,...
Jean-Luc Beuchat, Jean-Michel Muller
FCCM
1999
IEEE
111views VLSI» more  FCCM 1999»
14 years 3 months ago
Optimizing FPGA-Based Vector Product Designs
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
Dan Benyamin, John D. Villasenor, Wayne Luk
FPL
2009
Springer
91views Hardware» more  FPL 2009»
14 years 3 months ago
Large multipliers with fewer DSP blocks
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
Florent de Dinechin, Bogdan Pasca