105 search results - page 7 / 21 » Constant Multipliers for FPGAs |
ARC
2012
Springer
12 years 2 months ago
2012
Springer
Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing...
FPL
2010
Springer
13 years 5 months ago
2010
Springer
Abstract--Most current square root implementations for FPGAs use a digit recurrence algorithm which is well suited to their LUT structure. However, recent computing-oriented FPGAs ...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
FPGA
2004
ACM
14 years 13 days ago
2004
ACM
Moore’s Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important co...
CAI
2004
Springer
13 years 7 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...