Floorplanning in Modern FPGAs

State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oorplanning, the traditional algorithm for ASIC do not suf ce. In this paper, we have proposed an algorithm for uni ed oorplan topology generation and sizing for recent heterogeneous FPGAs. Experimental results on a set of benchmark circuits show that our three step oorplan generation method can produce feasible solutions very fast with 45% improvement in total half perimeter wirelength compared to the very few previous approaches.

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
• Keywords: Computer Architecture, Oorplan Topology Generation, State-of-the-art FPGA Architectures, Total Half Perimeter, VLSID 2007