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» Constrained Monte Carlo and the method of control variates
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DAC
2009
ACM
14 years 2 months ago
Variational capacitance extraction of on-chip interconnects based on continuous surface model
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increas...
Wenjian Yu, Chao Hu, Wangyang Zhang
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 25 days ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
IOLTS
2009
IEEE
124views Hardware» more  IOLTS 2009»
14 years 2 months ago
On-line characterization and reconfiguration for single event upset variations
The amount of physical variation among electronic components on a die is increasing rapidly. There is a need for a better understanding of variations in transient fault susceptibil...
Kenneth M. Zick, John P. Hayes
SLIP
2009
ACM
14 years 2 months ago
Closed-form solution for timing analysis of process variations on SWCNT interconnect
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
Peng Sun, Rong Luo
ICCAD
2005
IEEE
97views Hardware» more  ICCAD 2005»
14 years 4 months ago
DiCER: distributed and cost-effective redundancy for variation tolerance
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...