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» Constrainedness and Redundancy by Constraint Ordering
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ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
14 years 2 months ago
Mechanisms for bounding vulnerabilities of processor structures
Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance r...
Niranjan Soundararajan, Angshuman Parashar, Anand ...
CODES
2007
IEEE
14 years 2 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
ISSTA
2009
ACM
14 years 2 months ago
Precise pointer reasoning for dynamic test generation
Dynamic test generation consists of executing a program while gathering symbolic constraints on inputs from predicates encountered in branch statements, and of using a constraint ...
Bassem Elkarablieh, Patrice Godefroid, Michael Y. ...
TIT
2002
91views more  TIT 2002»
13 years 7 months ago
On limited-delay lossy coding and filtering of individual sequences
Abstract--We continue the study of adaptive schemes for the sequential lossy coding of individual sequences which was recently initiated by Linder and Lugosi. Specifically, we cons...
Tsachy Weissman, Neri Merhav
TASLP
2011
13 years 2 months ago
Time-Frequency Cepstral Features and Heteroscedastic Linear Discriminant Analysis for Language Recognition
Abstract—The shifted delta cepstrum (SDC) is a widely used feature extraction for language recognition (LRE). With a high context width due to incorporation of multiple frames, S...
Weiqiang Zhang, Liang He, Yan Deng, Jia Liu, M. T....