59 search results - page 8 / 12 » Constraint Analysis for DSP Code Generation |
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
TWC
2008
13 years 8 months ago
2008
In this paper the tradeoff between energy and delay for wireless networks is studied. A network using a request-to-send (RTS) and clear-to-send (CTS) type medium access control (M...
WWW
2004
ACM
14 years 9 months ago
2004
ACM
As Web sites are now ordinary products, it is necessary to explicit the notion of quality of a Web site. The quality of a site may be linked to the easiness of accessibility and a...
WCRE
2002
IEEE
14 years 1 months ago
2002
IEEE
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
PEPM
2009
ACM
15 years 8 months ago
2009
ACM
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...