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» Constraint Posting for Verifying VLSI Circuits
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IJCAI
1989
13 years 8 months ago
Constraint Posting for Verifying VLSI Circuits
We apply constraint posting to the problem of reasoning about function from structure. Constraint posting is a technique used by some planners to coordinate decisions. At each dec...
Daniel Weise
ATS
2010
IEEE
253views Hardware» more  ATS 2010»
13 years 5 months ago
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
Xiao Liu, Qiang Xu
DAC
2009
ACM
14 years 1 months ago
Information hiding for trusted system design
For a computing system to be trusted, it is equally important to verify that the system performs no more and no less functionalities than desired. Traditional testing and verifica...
Junjun Gu, Gang Qu, Qiang Zhou
ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
ISPD
2003
ACM
105views Hardware» more  ISPD 2003»
14 years 4 days ago
Partition-driven standard cell thermal placement
The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a scheme to achieve better thermal distribution for partitio...
Guoqiang Chen, Sachin S. Sapatnekar