A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Most current graph layout technology does not lend itself to interactive applications such as animation or advanced user interfaces. We introduce the constrained graph layout model...
In this contribution iteratively detected spatial division multiplexing is investigated under the constraint of a fixed data throughput. Existing bit loading and transmit power a...
Andreas Ahrens, Wei Liu, Soon Xin Ng, Volker K&uum...
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...
We propose a simple pulse-amplitude modulation (PAM)-based coded modulation scheme that overcomes two major constraints of power line channels, viz., severe insertion-loss and impu...