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» Constraint modules: An introduction
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DAC
2004
ACM
14 years 4 months ago
A timing-driven module-based chip design flow
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Fan Mo, Robert K. Brayton
CONSTRAINTS
1998
120views more  CONSTRAINTS 1998»
13 years 10 months ago
Constrained Graph Layout
Most current graph layout technology does not lend itself to interactive applications such as animation or advanced user interfaces. We introduce the constrained graph layout model...
Weiqing He, Kim Marriott
SIPS
2007
IEEE
14 years 5 months ago
SVD-Aided, Iteratively Detected Spatial Division Multiplexing Using Long-Range Channel Prediction
In this contribution iteratively detected spatial division multiplexing is investigated under the constraint of a fixed data throughput. Existing bit loading and transmit power a...
Andreas Ahrens, Wei Liu, Soon Xin Ng, Volker K&uum...
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
14 years 5 months ago
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Ko...
JSAC
2006
108views more  JSAC 2006»
13 years 11 months ago
A simple baseband transmission scheme for power line channels
We propose a simple pulse-amplitude modulation (PAM)-based coded modulation scheme that overcomes two major constraints of power line channels, viz., severe insertion-loss and impu...
Raju Hormis, Inaki Berenguer, Xiaodong Wang