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ICIP
2008
IEEE
14 years 4 months ago
Time-sequential extraction of motion layers
A new time-sequential approach for motion layer extraction is presented. We assume that the scene can be described by a set of layers associated to affine motion models. In one o...
Matthieu Fradet, Patrick Pérez, Philippe Ro...
CONCUR
2004
Springer
14 years 3 months ago
Model Checking Timed Automata with One or Two Clocks
In this paper, we study model checking of timed automata (TAs), and more precisely we aim at finding efficient model checking for subclasses of TAs. For this, we consider model ch...
François Laroussinie, Nicolas Markey, Ph. S...
FPL
2001
Springer
107views Hardware» more  FPL 2001»
14 years 2 months ago
Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays
In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation o...
John Karro, James P. Cohoon
DAC
1996
ACM
14 years 2 months ago
Characterization and Parameterized Random Generation of Digital Circuits
The development of new Field-Programmed, MaskProgrammed and Laser-Programmed Gate Array architectures is hampered by the lack of realistic test circuits that exercise both the arc...
Michael D. Hutton, Jerry P. Grossman, Jonathan Ros...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
14 years 1 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu