This paper surveys recent results in the area of virtual path layout in ATM networks. We present a model for the theoretical study of these layouts the model amounts to covering t...
We present a framework for solving multistage pure 0–1 programs for a widely used sequencing and scheduling problem with uncertainty in the objective function coefficients, the...
Antonio Alonso-Ayuso, Laureano F. Escudero, M. Ter...
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...
We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is appli...
— In this paper we present an automated support for software model evolution using a formal language constructs. For this, we extended Object Constraint Language (OCL) with actio...