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ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Managing verification error traces with bounded model debugging
Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior...
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
CLIMA
2010
14 years 10 days ago
Combining Logics in Simple Type Theory
Simple type theory is suited as framework for combining classical and non-classical logics. This claim is based on the observation that various prominent logics, including (quantif...
Christoph Benzmüller
AIEDAM
1999
157views more  AIEDAM 1999»
13 years 10 months ago
Representing a robotic domain using temporal description logics
A temporal logic for representing and reasoning on a robotic domain is presented. Actions are represented by describing what is true while the action itself is occurring, and plan...
Alessandro Artale, Enrico Franconi
SLOGICA
2010
97views more  SLOGICA 2010»
13 years 9 months ago
An Internal Version of Epistemic Logic
Abstract. Representing an epistemic situation involving several agents obviously depends on the modeling point of view one takes. We start by identifying the types of modeling poin...
Guillaume Aucher
AAAI
2011
12 years 11 months ago
Abductive Markov Logic for Plan Recognition
Plan recognition is a form of abductive reasoning that involves inferring plans that best explain sets of observed actions. Most existing approaches to plan recognition and other ...
Parag Singla, Raymond J. Mooney