Managing verification error traces with bounded model debugging

Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior which drastically limits their application. This work presents Bounded Model Debugging, an iterative, systematic and practical methodology to allow debuggers to tackle larger problems than previously possible. Based on the empirical observation that errors are excited in temporal proximity of the observed failures, we present a framework that improves performance by up to two orders of magnitude and solve 2.7

• Type: Journal
• Year: 2010
• Where: ASPDAC
• Authors: Sean Safarpour, Andreas G. Veneris, Farid N. Najm
• Keywords: ASPDAC 2010, Debugger, Hardware, Iterative Logic Array, Long Verification