94 search results - page 15 / 19 » Control Independence in Trace Processors |
HASE
1999
IEEE
13 years 11 months ago
1999
IEEE
The state of the art in verifying the real-time requirements of applications developed using general processing graph models relies on simulation or off-line scheduling. We extend...
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
ASPLOS
2010
ACM
13 years 10 months ago
2010
ACM
Many parallel applications exhibit unpredictable communication between threads, leading to contention for shared objects. The choice of contention management strategy impacts stro...
OSDI
2002
ACM
14 years 7 months ago
2002
ACM
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...
CORR
2011
Springer
12 years 11 months ago
2011
Springer
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated p...