94 search results - page 16 / 19 » Control Independence in Trace Processors |
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
ISW
2009
Springer
14 years 2 months ago
2009
Springer
We present ShMAC (Shallow MAC), a fixed input length message authentication code that performs most of the computation prior to the availability of the message. Specifically, Sh...
RTSS
2006
IEEE
14 years 1 months ago
2006
IEEE
We present an optimal real-time scheduling algorithm for multiprocessors — one that satisfies all task deadlines, when the total utilization demand does not exceed the utilizat...
HOTI
2005
IEEE
14 years 1 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...