94 search results - page 6 / 19 » Control Independence in Trace Processors |
ICANN
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project,...
ICCD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...