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» Control flow optimization in loops using interval analysis
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CODES
2004
IEEE
13 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
BIOINFORMATICS
2005
152views more  BIOINFORMATICS 2005»
13 years 6 months ago
Intervention in context-sensitive probabilistic Boolean networks
Motivation: Intervention in a gene regulatory network is used to help it avoid undesirable states, such as those associated with a disease. Several types of intervention have been...
Ranadip Pal, Aniruddha Datta, Michael L. Bittner, ...
RTAS
2010
IEEE
13 years 5 months ago
Scheduling Self-Suspending Real-Time Tasks with Rate-Monotonic Priorities
Abstract—Recent results have shown that the feasibility problem of scheduling periodic tasks with self-suspensions is NPhard in the strong sense. We observe that a variation of t...
Karthik Lakshmanan, Ragunathan Rajkumar
PVLDB
2008
98views more  PVLDB 2008»
13 years 6 months ago
Performance profiling with EndoScope, an acquisitional software monitoring framework
We propose EndoScope, a software monitoring framework that allows users to pose declarative queries that monitor the state and performance of running programs. Unlike most existin...
Alvin Cheung, Samuel Madden
DAC
2005
ACM
14 years 7 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...