Sciweavers

58 search results - page 4 / 12
» Controlled-Load Limited Switch Dynamic Logic Circuit
Sort
View
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 8 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 5 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou
ICPADS
2008
IEEE
14 years 1 months ago
Dynamic Resource Allocation in Enterprise Systems
It is common that Internet service hosting centres use several logical pools to assign server resources to different applications, and that they try to achieve the highest total r...
James Wen Jun Xue, Adam P. Chester, Ligang He, Ste...
DAC
2005
ACM
14 years 8 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 11 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght