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AEI
2008
108views more  AEI 2008»
13 years 7 months ago
Combinatorial synthesis approach employing graph networks
The paper proposes a methodology to assist the designer at the initial stages of the design synthesis process by enabling him/her to employ knowledge and algorithms existing in gr...
Offer Shai, Noel Titus, Karthik Ramani
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
13 years 11 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
14 years 1 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
ACSC
2000
IEEE
13 years 11 months ago
Object-Oriented Natural Language Requirements Specification
A methodology is proposed for the formal development of software systems from a user's requirements specification in natural language into a complete implementation, proceedi...
Barrett R. Bryant
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Floorplan management: incremental placement for gate sizing and buffer insertion
Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental ch...
Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden