28 search results - page 3 / 6 » Convex delay models for transistor sizing |
TCAD
2008
13 years 7 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
ICCAD
1995
IEEE
13 years 10 months ago
1995
IEEE
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
PATMOS
2005
Springer
14 years 14 days ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
ASPDAC
2006
ACM
14 years 29 days ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
WIOPT
2010
IEEE
13 years 4 months ago
2010
IEEE
In this paper, we investigate the stability and delay issues of a two-user multi-access channel at the bit level. The two users, have the option to transmit at a higher rate (measu...