In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
—In this paper we propose two advanced algorithms which allow for both differentiated quality-of-service (QOS) and power conservation in input-queued packet switches. These algor...
Benjamin Yolken, Dimitrios Tsamis, Nicholas Bambos
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Abstract— Research on context-aware systems is usually usercentric and thus focussed on the context of a specific user to serve his or her needs in an optimized way. In this pap...