275 search results - page 15 / 55 » Core architecture optimization for heterogeneous chip multip... |
JSA
2007
13 years 8 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
DAMON
2006
Springer
14 years 10 days ago
2006
Springer
A new trend in processor design is increased on-chip support for multithreading in the form of both chip multiprocessors and simultaneous multithreading. Recent research in databa...
JSA
2008
13 years 8 months ago
2008
As chip multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors. In this paper, performance measurement...