275 search results - page 29 / 55 » Core architecture optimization for heterogeneous chip multip... |
CCECE
2006
IEEE
14 years 2 months ago
2006
IEEE
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
CASES
2009
ACM
14 years 3 months ago
2009
ACM
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
ET
2002
13 years 8 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
ISQED
2010
IEEE
13 years 7 months ago
2010
IEEE
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...